HD6433937 Datasheet, PDF (393/521 Pages) Hitachi Semiconductor – Hardware Manual

packets decrement the count for the first fragment and the last fragment. This dec-rements the
all frame counter to zero, if no other fragmented messages, temporary addresses are pending
and the FAF bit is clear in the All Frame Mode Register, the FLEX decoder returns to normal
operation.
• The above process must be repeated for each occurrence of a fragmented message. The host
must keep track of the number of fragmented messages being decoded and insure the all frame
mode counter decrements after each fragment or after each fragmented message.
Table 12-32 Alphanumeric Message without fragmentation
PACKET
All Frame
PACKET TYPE PHASE Counter COMMENT
1st
ADDRESS 1
A
0
Address 1 is received
2nd
VECTOR 1
A
1
Vector = Alphanumeric Type
3rd
MESSAGE
A
1
Message Word received “C” bit = 0, No
more fragments are expected.
4th
Variable*
0
Host writes All Frame Mode Packet to the
FLEX decoder with the “DAF” bit = 1
Note: * Host Initiated Packet. The FLEX decoder returns a packet according to 12.4, Decoder-
to-Host Packet Descriptions.
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