HD6433937 Datasheet, PDF (17/521 Pages) Hitachi Semiconductor – Hardware Manual

1.2 Internal Block Diagram
Figure 1-1 shows a block diagram of the H8/3937 Series and H8/3937R Series.
P10/TMOW
P11/TMOFL
P12/TMOFH
P13/TMIG
P14/IRQ4/ADTRG
P15/IRQ1/TMIC
P16/IRQ2
P17/IRQ3/TMIF
P30
P31/UD
P32/RESO
P33/SCK31
P34/RXD31
P35/TXD31
P36
P37
P50/WKP0
P51/WKP1
P52/WKP2
P53/WKP3
P54/WKP4
P55/WKP5
P56/WKP6
P57/WKP7
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
ROM
(60 k, 48 k, 40 k)
H8/300L
CPU
RAM
(2 k)
Timer-A
Timer-C
Serial
communication
interface 31
Timer-F
Timer-G
Serial
communication
interface 32
WDT
A/D (10-bit)
Port 4
Internal functions
Serial
communication
interface 1
Port 2
Internal
I/O port
TEST20
TEST21
TEST22
TEST23
TEST24
TEST43
PA3
PA2
PA1
PA0
P93
P92
P91
P90
P87
P86
P85
P84
P83
P82
P81
P80
P77
P76
P75
P74
P73
P72
P71
P70
P67
P66
P65
P64
P63
P62
P61
P60
FLEX™ decoder
Note: Serial communication interface 1, P2₀ to P2₄, and P4₃, are internal functions that perform interfacing to
the FLEX™ decoder incorporated in the chip.
Figure 1-1 Block Diagram
5