HD6433937 Datasheet, PDF (79/521 Pages) Hitachi Semiconductor – Hardware Manual

Bit 4: Timer G interrupt enable (IENTG)
Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Bit 4
IENTG
0
1
Description
Disables timer G interrupt requests
Enables timer G interrupt requests
(initial value)
Bit 3: Timer FH interrupt enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH
0
1
Description
Disables timer FH interrupt requests
Enables timer FH interrupt requests
(initial value)
Bit 2: Timer FL interrupt enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL
0
1
Description
Disables timer FL interrupt requests
Enables timer FL interrupt requests
(initial value)
Bit 1: Timer C interrupt enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC
0
1
Description
Disables timer C interrupt requests
Enables timer C interrupt requests
(initial value)
Bit 0: Reserved bit
Bit 0 is reserved: it is always read as 0 and cannot be modified.
For details of SCI31 interrupt control, see 6. Serial control register 3 (SCR3) in section 10.3.2.
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