HD6433937 Datasheet, PDF (351/521 Pages) Hitachi Semiconductor – Hardware Manual

1F is sent to the decoder IC, the value sent in the 24 information bits is exclusive-or’ed with the
internal checksum register, the result is stored back to the checksum register, and the FLEX
decoder is disabled. If a Checksum Packet is sent and the CV bits match the bits in the checksum
register, the FLEX decoder is enabled. If a Checksum Packet is sent when the FLEX decoder is
already enabled, the packet is ignored by the FLEX decoder. If a packet other than the Checksum
Packet is sent when the FLEX decoder is enabled, the decoder IC will be disabled until a
Checksum Packet is sent with the correct CV bits.
When the host reads a packet out of the FLEX decoder but has no data to send, the Checksum
Packet should be sent so the FLEX decoder will not be disabled. The data in the Checksum Packet
could be a null packet (32 bit stream of all zeros) since a Checksum Packet will not disable the
FLEX decoder. When the host re-configures the FLEX decoder, the FLEX decoder will be
disabled from sending any packets other than the Part ID Packet until the FLEX decoder is
enabled with a Checksum Packet having the proper data. The ID of the Checksum Packet is 0.
Table 12-3 Checksum Packet Bit Assignments
Bit 7
Bit 6
Byte 3 0
0
Byte 2 CV₂₃
CV ₂₂
Byte 1 CV₁₅
CV ₁₄
Byte 0 CV₇
CV₆
CV: Checksum Value.
Bit 5
0
CV ₂₁
CV ₁₃
CV₅
Bit 4
0
CV ₂₀
CV ₁₂
CV₄
Bit 3
0
CV ₁₉
CV ₁₁
CV₃
Bit 2
0
CV ₁₈
CV ₁₀
CV₂
Bit 1
0
CV ₁₇
CV₉
CV₁
Bit 0
0
CV ₁₆
CV₈
CV₀
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