HD6433937 Datasheet, PDF (483/521 Pages) Hitachi Semiconductor – Hardware Manual

IENR1—Interrupt enable register 1
H'F3
System control
Bit
Initial value
Read/Write
7
IENTA
0
R/W
6
IENS1
0
R/W
5
IENWP
0
R/W
4
IEN4
0
R/W
3
IEN3
0
R/W
2
IEN2
0
R/W
1
IEN1
0
R/W
0
IEN0
0
R/W
IRQ₄ to IRQ₀ interrupt enable
0 Disables IRQ₄ to IRQ₀ interrupt requests
1 Enables IRQ₄ to IRQ₀ interrupt requests
Note: IRQ₀ is an internal signal that performs
interfacing to the FLEX™ decoder incorporated
in the chip.
Wakeup interrupt enable
0 Disables WKP₇ to WKP₀ interrupt requests
1 Enables WKP₇ to WKP₀ interrupt requests
SCI1 interrupt enable
0 Disables SCI1 interrupt requests
1 Enables SCI1 interrupt requests
Note: SCI1 is an internal function that performs
interfacing to the FLEX™ decoder
incorporated in the chip.
Timer A interrupt enable
0 Disables timer A interrupt requests
1 Enables timer A interrupt requests
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