HD6433937 Datasheet, PDF (342/521 Pages) Hitachi Semiconductor – Hardware Manual

the proper FLEX channel, and fully interpreting the code words that are passed to the host from
the FLEX decoder.
Additional Information: Additional Information on the FLEX^TM protocol decoder chip set and
FLEXstack™ software can be found at the following website:
http://www.hitachi.co.jp/Sicd/English/Products/micom/stack/stack.html.
12.1.2 System Block Diagram
Synthesizer Programming Control
Receiver
Receiver
Control
S0/IFIN
This LSI
User
Interface
38.4 or 40 kHz clock
Low Battery
Detector
LOBAT
160 kHz Oscillator
Figure 12-1 Example Block Diagram Using Internal Demodulator
When configured to use the internal demodulator, the FLEX decoder connects to a receiver
capable of generating a limited (i.e. 1-bit digitized) 455 kHz or 140 kHz IF signal. In this mode,
the FLEX decoder has 7 receiver control lines used for warming up and shutting down a receiver
in stages. The FLEX decoder has the ability to detect a low battery signal during the receiver
control sequences. It interfaces to a host MCU through a standard SPI. It has a 1 minute timer that
offers low power support for a time of day function on the host.
When using the internal demodulator, the oscillator frequency (or external clock) must be 160
kHz. The CLKOUT signal can be programmed to be either a 38.4 kHz signal created by
fractionally dividing the oscillator clock, or a 40 kHz signal creating by dividing the oscillator
clock by 4.
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