HD6433937 Datasheet, PDF (82/521 Pages) Hitachi Semiconductor – Hardware Manual

Bit 6: A/D converter interrupt request flag (IRRAD)
Bit 6
IRRAD
0
1
Description
Clearing conditions:
When IRRAD = 1, it is cleared by writing 0
(initial value)
Setting conditions:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Bit 5: Reserved bit
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Bit 4: Timer G interrupt request flag (IRRTG)
Bit 4
IRRTG
0
1
Description
Clearing conditions:
When IRRTG = 1, it is cleared by writing 0
(initial value)
Setting conditions:
When the TMIG pin is designated for TMIG input and the designated signal edge is
input, and when TCG overflows while OVIE is set to 1 in TMG
Bit 3: Timer FH interrupt request flag (IRRTFH)
Bit 3
IRRTFH
0
1
Description
Clearing conditions:
When IRRTFH = 1, it is cleared by writing 0
(initial value)
Setting conditions:
When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH)
and OCRF (OCRFL, OCRFH) match in 16-bit timer mode
Bit 2: Timer FL interrupt request flag (IRRTFL)
Bit 2
IRRTFL
0
1
Description
Clearing conditions:
When IRRTFL= 1, it is cleared by writing 0
Setting conditions:
When TCFL and OCRFL match in 8-bit timer mode
(initial value)
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