HD6433937 Datasheet, PDF (111/521 Pages) Hitachi Semiconductor – Hardware Manual

Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0)
These bits designate the time the CPU and peripheral modules wait for stable clock operation after
exiting from standby mode or watch mode to active mode due to an interrupt. The designation
should be made according to the operating frequency so that the waiting time is at least equal to
the oscillation settling time.
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0
Description
0
0
0
Wait time = 8,192 states
(initial value)
0
0
1
Wait time = 16,384 states
0
1
0
Wait time = 1,024 states
0
1
1
Wait time = 2,048 states
1
0
0
Wait time = 4,096 states
1
0
1
Wait time = 2 states
(External clock input mode)
1
1
0
Wait time = 8 states
1
1
1
Wait time = 16 states
Note: When inputting the external clock, set the standby timer select to the external clock input
mode. Also, when not using the external clock, do not set the standby timer select to the
external clock input mode.
Bit 3: Low speed on flag (LSON)
This bit chooses the system clock (ø) or subclock (ø_SUB) as the CPU operating clock when watch
mode is cleared. The resulting operation mode depends on the combination of other control bits
and interrupt input.
Bit 3
LSON
0
1
Description
The CPU operates on the system clock (ø)
The CPU operates on the subclock (ø_SUB)
(initial value)
Bit 2: Reserved bit
Bit 2 is reserved: it is always read as 1 and cannot be modified.
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