HD6433937 Datasheet, PDF (304/521 Pages) Hitachi Semiconductor – Hardware Manual

Start receive
4 _{error processing}
Yes
OER = 1?
No
Yes
FER = 1?
No
Yes
PER = 1?
Overrun error
processing
Break?
No
Framing error
processing
No
Clear bits OER, PER,
FER to 0 in SSR
Parity error
processing
4. If a receive error has
occurred, read bits OER,
PER, and FER in SSR to
identify the error, and after
carrying out the necessary
error processing, ensure
that bits OER, PER, and
Yes
FER are all cleared to 0.
Reception cannot be
resumed if any of these
bits is set to 1. In the case
of a framing error, a break
can be detected by reading
the value of the RXD_3x pin.
(A)
End of receive
error processing
Figure 10-10 Example of Data Reception Flowchart (Asynchronous Mode) (cont)
292