HD6433937 Datasheet, PDF (118/521 Pages) Hitachi Semiconductor – Hardware Manual

Table 5-4 Clock Frequency and Settling Time (times are in ms)
STS2
0
0
0
0
1
1
1
1
STS1
0
0
1
1
0
0
1
1
STS0
0
1
0
1
0
1
0
1
Waiting Time
8,192 states
16,384 states
1,024 states
2,048 states
4,096 states
2 states (not available)
8 states
16 states
5 MHz
1.6384
3.2768
0.2048
0.4096
0.8192
0.0004
0.0016
0.0032
2 MHz
4.096
8.192
0.512
1.024
2.048
0.001
0.004
0.008
1 MHz
8.192
16.384
1.024
2.048
4.096
0.002
0.008
0.016
• When an external clock is used
STS2 = 1, STS1 = 0 and STS0 = 1 are recommended. Other values can be set, but with other
settings, operation may start before the standby time is over.
5.3.4 Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is
cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the high-
impedance state (except pins for which the pull-up MOS is designated as on). Figure 5-2 shows
the timing in this case.
ø
Internal data bus
SLEEP instruction fetch Fetch of next instruction
SLEEP instruction execution Internal processing
Pins
Port output
High-impedance
Active (high-speed) mode or active (medium-speed) mode
Standby mode
Figure 5-2 Standby Mode Transition and Pin States
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