CD2481 Datasheet, PDF (98/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
To be validated, a condition must be present for two character times with a stable value on the
CTS* pin (CTS* is used in X.21 as the ‘I’ lead in a DTE or ‘C’ lead in a DCE).
For X.21, the SSDE bit (COR3[6]) must be set to enable the detection of the steady state
conditions; this enables the detection of the all ‘1’s, all ‘0’s and the alternating ‘1’s and ‘0’s
conditions with a stable value on the CTS* pin. When the SSDE bit is set, the StrpSyn and SCDE
bits (COR3[5:4]) can also be set, if required (if SSDE is not set then the StrpSyn and SCDE bits
have no effect).
Note: The SglSyn bit COR3[7] must be ‘0’ because X.21 mode always requires two SYN characters for
synchronization.
Enable the SSDE and StrpSYN bits to prevent SYN characters from entering the receive data
FIFO. When set, the StrpSYN bit treats SYN characters the same way as steady-state conditions
(that is, when two valid SYN characters are detected, a receive special character interrupt is
generated and the next SYN characters are stripped from the incoming data stream). If the
StrpSYN bit is not set, the SYN character is still used to achieve character synchronization, but all
received SYN characters are passed to the CPU as normal receive data.
The SCDE bit enables the detection of the special characters defined in SCHR1–3 the same way as
steady-state conditions. When detected for two consecutive character times, a special character
detect interrupt is generated and the next repetitions of the same character are stripped from the
receive data (for example, to detect the ‘BEL off’ condition for a DTE incoming call, then strip that
repetition until the next state change). Character synchronization must be achieved before SCHR1–
3 can be detected.
In certain phases of X.21 call setup, there is no character synchronization. When a data change
occurs in a non-character synchronous phase, a partial character can be detected before the steady
is detected or character sync is achieved. In these conditions, the partial character is passed to the
host as normal data.
Note: The CD2481 passes all data it receives to the host prior to receiving SYN characters.
Example:
Assume SSDE, StrpSyn, and SCDE bits in COR3 are set, i.e., the CD2481 detects steady-state
conditions, strip SYN and special characters from the incoming data. Under these conditions, the
following data stream:
Incoming Data:
SS SS Junk SS SS SYN SYN Bell Bell Data Data SS SS
Where SS = Steady State Condition.
Note: A SYN Character Detect interrupt is generated after the second SYN. A Special Character Detect
interrupt is generated after the second Bell
The incoming data is passed to the host as follows:
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Datasheet