CD2481 Datasheet, PDF (193/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
9.6.5.9
Append mode, the CD2481 does not set the EOB bit. When the host has completed use of the
buffer, it must issue the append complete command through STCR. The CD2481, upon
transmitting the last characters from the buffer, sets EOB, thus allowing the host to allocate a new
transmit buffer.
A Transmit Buffer Status (ATBSTS) –HDLC / Bisync / X.21 Modes
Register Name: ATBSTS
Register Description: Transmit Buffer ‘A’ Status Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Berr
EOF
EOB
UE
Bit 3
0
Intel Hex Address: x’5C
Motorola Hex Address: x’5F
Bit 2
0
Bit 1
INTR
Bit 0
2481own
9.6.5.10 B Transmit Buffer Status (BTBSTS) –HDLC / Bisync / X.21 Modes
Register Name: BTBSTS
Register Description: Transmit Buffer ‘B’ Status Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Berr
EOF
EOB
UE
Bit 3
0
Bit 2
0
Intel Hex Address: x’5D
Motorola Hex Address: x’5E
Bit 1
INTR
Bit 0
2481own
These registers contain the status of the associated transmit buffer, and enables successive buffers
to be passed between the host and the CD2481. Status bits within the register are defined as:
Bit 7
Bus error (set by the CD2481 and cleared by the host CPU)
0 = no bus error
1 = bus error occurred on the last transfer; the suspect address is available in
TCBADR
Bit 6
End of frame (set and cleared by host CPU)
0 = this buffer is not the last in frame/block
1 = this buffer is the last in frame/block
Bit 5
End of a transmit buffer has been reached. Used only for DMA supported transfer.
The end of one of the host supplied transmit buffers has been reached. This bit is set
by the CD2481 and cleared by the host CPU.
Bit 4
Underrun – Transmit underrun occurred as the buffer was not available, and it
applies to this buffer.
Bit 3:2
Reserved – must be zero.
Bit 1
Interrupt
0 = no interrupt required after the buffer is sent
1 = interrupt required after the buffer is sent
Datasheet
193