CD2481 Datasheet, PDF (178/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
9.5.3.6
in Section 8.4 for positioning valid data on the bus. If the BYTESWAP pin is high, data must be
valid on A/D[0–7]; if BYTESWAP is low, data must be valid on A/D[8–15], because the TDR is on
an even address.
Transmit End of Interrupt Register (TEOIR)
Register Name: TEOIR
Register Description: Transmit End of Interrupt Register
Default Value: x’00
Access: Byte Write Only
Bit 7
Bit 6
Bit 5
Bit 4
TermBuff
EOF
SetTm2
SetTm1
Bit 3
Notrans
Intel Hex Address: x’86
Motorola Hex Address: x’85
Bit 2
0
Bit 1
0
Bit 0
0
The Transmit End of Interrupt register must be written to by the corresponding host interrupt
service routine to signal to the CD2481 that the current interrupt service is concluded. This must be
the last access to the CD2481 during an interrupt service routine. Writing to this register generates
an internal end of interrupt signal which pops the CD2481 interrupt context stack.
Depending on the circumstances of an individual interrupt service, the host can be required to pass
a parameter to the CD2481 through these registers.
Bit 7
1 = Terminate buffer in DMA mode forces the current buffer to be discarded.
Note: If current interrupt is a transmit end-of-buffer interrupt, setting this bit at the end of the service
routine causes the next buffer to be terminated also.
Bit 6
End of frame in Synchronous modes using interrupt-driven data transfer
0 = this data transfer does not complete the frame/block.
1 = this data transfer does complete the frame/block.
Bit 5
Set general timer 2 (Synchronous modes only)
0 = do not set general timer 2.
1 = load the value, provided in TISR, to general timer 2.
Bit 4
Set general timer 1 (Synchronous modes only)
0 = do not set general timer 1.
1 = load the value, provided in TISR, to the high byte of general timer 1.
At the end of an interrupt service routine, the user can set a timer by setting a timer
value in the Transmit Interrupt Status register. When the timer reaches ‘0’, the
CD2481 generates a modem/timer group interrupt to the host.
Bit 3
No transfer of data
This bit must be set by the host, if no data is transferred to the transmit FIFO during
a data transfer interrupt.
Bits 2:0
Reserved – must be zero.
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Datasheet