CD2481 Datasheet, PDF (101/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
7.9.1
7.9.2
stream via either one or two user defined SYN characters. Additionally, up to four frame
terminating (EOF) characters can be defined. The transmitter may be programmed to idle the
transmit data line in either an active high or active low condition; there is no flag fill option in this
mode.
Programmable Sync Transmit
The transmitter sends the frame data, shifted out LSB first, with no start or stop bits, no bit-stuffing
and no frame check sequence (FCS). This allows maximum flexibility to implement protocols that
have non-standard CRC polynomials. If the special protocol being implemented uses an FCS, the
host must compute and append the check characters to the frame prior to transmission.
If the character length is less than 8 bits, the CD2481 will strip the unused MSB bits from the
character prior to transmission so that the data stream remains true to the character length selected.
Between frames, the CD2481 can ‘idle’ the TxD pin in either a continuous ‘1’ or ‘0’, depending on
the setting of the Idle bit (COR1[7]).
If an underrun condition occurs, either from DMA latency or lack of a buffer (in chained buffer
instances) or due to the host failing to respond to a transmit data interrupt in time, the transmitter
immediately aborts transmission of the frame and returns the transmit data line to the programmed
idle condition.
The host signals the end of frame via either setting the EOF bit in the TEOIR register (interrupt
mode) or via the EOF bit in the A/BTBSTS registers (DMA mode).
Programmable Sync Receive
Receive characters are assembled LSB first, with the MSB bits filled with zeroes if the number of
bits per character is less than eight.
The receiver initially enters SYN-hunt mode when enabled via the receiver enable command of the
CCR. It will shift in data, comparing the value with sync character (SYN1), as specified by the
value programmed in COR6. The match is performed on the number of LSB bits programmed for
the character length (COR1[3:0]). After character synchronization is achieved via match against
SYN1, COR2 is examined to determine if SYN1-SYN2 mode is enabled (COR2[7]). If SYN1-only
mode is selected, frame reception commences and, if Strip is enabled (COR2[6]), SYN1 is
discarded and not included in the frame data presented to the host, otherwise it is included in the
data stream.
If SYN1-SYN2 mode is enabled, the character immediately following SYN1 is compared against
the SYN2 value, as programmed in COR7. If a match occurs on SYN2, frame reception begins,
with stripping as enabled. If the second character does not match SYN2, the receiver reverts to
SYN-hunt mode.
Up to four separate characters may be programmed as frame terminating (EOF) flags. These EOF
characters are programmed via the four Special Character Registers (SCHR1-SCHR4). If fewer
than four EOF characters are needed, the values in the unused SCHR registers should be
programmed with duplicates of the values in use. That is, if only one EOF is needed, all four SCHR
registers should be programmed with the same EOF value; if two are needed, SCHR1 and SCHR2
should contain the two characters and SCHR3 and SCHR4 should have duplicates of those values.
Once the EOF has been detected, the receiver will automatically re-enter SYN-hunt mode.
Datasheet
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