CD2481 Datasheet, PDF (58/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
5.4.7.4
5.4.7.5
5.4.7.6
Append Mode
The Append mode reduces the CPU overhead required to provide asynchronous terminal echoing
functionality; this is also necessary for any similar application that involves an unpredictable data
stream. The A buffer can be set into Append mode by the ATBSTS register. This buffer can then
be used for the echoed data, while the B buffer is used for all other output data. The append buffer
allows data transmission to start from a buffer before all the data is available for transmission. For
example, terminal echoing requires that each character is echoed (or translated and echoed) before
the complete line is typed.
To operate in Append mode, the ATBADR and ATBCNT would be set as normal (the ATBCNT
can be zero), and the 2481OWN and the Append bit set in the ATBSTS. When any data is available
for transmission, it is placed in the RAM buffer by the CPU, and the total buffer byte count is
updated in the ATBCNT. The CD2481 now scans the ATBCNT register for any changes; if new
data is found, it is read from the buffer and transmitted.
When no more data is found in the append buffer, the CD2481 scans the B buffer for ownership. If
the B buffer is owned by the CD2481, then the data in that buffer is transmitted uninterrupted; at
the end of the transmission, the A buffer count continues to be scanned for new data.
For correct operation of this feature, the ATBCNT register should be updated with a word write
operation. If only byte access is possible, the value should not exceed 256 bytes. This mode allows
multiple transfers to be performed through a single buffer; it saves CPU overhead by either
processing multiple buffers or in handling interrupts with every character.
Line retransmission becomes as simple as ‘stepping back’ in the buffer and resending. To terminate
the Append mode, a command can be given by the STCR register that causes the A buffer to be
terminated when all current data has been sent.
Transmit Bus Errors
When a transmit bus error interrupt is generated, the TISR and A/BTBSTS registers both indicate a
bus error status. The current transfer address is available in the TCBADR[0–3] registers, and the
bus error occurred on the last transfer that started at this address. This means the actual error
address can be up to 16 bytes further in the buffer.
Following a bus error condition, the CPU has the choice of either discontinuing the current buffer
or retrying from the start of the last transfer. To discontinue, the current buffer and the TermBuff
bit should be set when TEOIR is written to at the end of the interrupt. In Synchronous mode, the
frame is still in progress and needs to be aborted by the Special Transmit Command register
(STCR).
To retry the frame, the CPU should set the 2481OWN bit in the ATBSTS/BTBSTS register, and
not set the TermBuff bit when writing to TEOIR at the end of the interrupt. This causes the last
transfer to be retried; should a bus error occur again, the above procedure is repeated. The CPU
should check to ensure that a bad location is not continually retried.
Receive Buffer Interrupts
When a receive buffer is complete, the CD2481 generates an end-of-frame receive exception
interrupt. It provides the CPU with RISR status and information on which buffer is complete.
58
Datasheet