CD2481 Datasheet, PDF (167/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
Bit 2:0
the receiver buffer and/or FIFO. The OE status is set on the last character received
before the overrun occurred.
Reserved – returns ‘0’ when read.
Note: During an interrupt service routine, the host can use this register to provide a timer value as
detailed in the Receive End of Interrupt register. The host can only load one of the two timers in the
interrupt service routine.
RISRl – Asynchronous Mode
Register Name: RISRl
Register Description: Receive Interrupt Status Register - Low
Default Value: x’00
Access: Byte Read Only
Bit 7
Bit 6
Bit 5
Bit 4
Timeout
SCdet2
SCdet1
SCdet0
Bit 3
OE
Bit 2
PE
Intel Hex Address: x’8A
Motorola Hex Address: x’89
Bit 1
FE
Bit 0
Break
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Binary Value for Timer
Bit 2
Bit 1
Bit 0
If RxData in IER is set, these interrupts are enabled.
Bit 7
Timeout – indicates that the receive FIFO is empty, and no data has been received
within the receive time-out period. There is no data character associated with this
status, and no other status bits are valid if the Time-Out bit is set.
Bits 6:4
Special character detect
Bit 3
Bit 2
SCdet[2:0]
Status
000
None detected
001
Special Character 1 matched
010
Special Character 2 matched
011
Special Character 3 matched (only if ESCDE is enabled in COR3)
100
Special Character 4 matched (only if ESCDE is enabled in COR3)
Character is within the inclusive range of the characters in the Special
111
Character Range low and high registers (only if RngDE is enabled in
COR3). Special character match can be enabled for error characters by
COR7.
Overrun error – indicates that new data has arrived, but the CD2481 FIFO or holding
registers are full. The new data is lost and the overrun indication is flagged on the
last character received before the overrun occurred.
Parity error – indicates that a parity error has occurred.
Datasheet
167