CD2481 Datasheet, PDF (17/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
Table 1. Pin Descriptions (Sheet 1 of 3)
Symbol
CS*
AS*
DS*
R/W*
DTACK*
SIZ[0–1]
Type
I
I/O (TS)
I/O (TS)
I/O (TS)
I/O (OD)
I/O (TS)
Description
CHIP SELECT*: When low, the CD2481 registers may be read from or written to by the host
processor.
ADDRESS STROBE*: When the CD2481 is a bus master, this pin is an output, which indicates
that R/W*, A[0–7], and the externally latched A[8–31] are valid.
DATA STROBE*: When the CD2481 is not a bus master, this is an input used to strobe data
into registers during write cycles and enable data onto the bus during read cycles. When the
CD2481 is a bus master, DS* is an output used to control data transfer to and from system
memory.
READ/WRITE*: When the CD2481 is not a bus master, this pin is an input which determines if a
read or write operation is required when the CS* and DS* signals are active. When the CD2481
is a bus master, R/W* is an output and indicates whether a read from or a write to system
memory is being performed.
DATA TRANSFER ACKNOWLEDGE*: When the CD2481 is not a bus master, this is an output
and indicates to the host when a read or write to the CD2481 is complete. When BR* is driven
low by the CD2481, DTACK* is an input, which indicates that the system bus is no longer in use.
When the CD2481 is a bus master, DTACK* is an input, which indicates when system memory
read and write cycles are complete.
SIZE [0–1]: When not the active bus master, these are inputs which determine the size of the
operand being read or written by the host.
SIZ[1] SIZ[0]
0
1
- Byte *
1
0
- 16 Bit
0
0
- 32 Bit **
1
1
- 3 Bytes**
When the CD2481 is a bus master, this is an output determining the size of the operand being
transferred to or from system memory.
SIZ[1] SIZ[0]
0
1
- Byte *
1
0
- 16 Bit
IACKIN*
IACKOUT*
IREQ*[1–3]
BR*
BGIN*
BGOUT*
BGACK*
I
O
I/O (OD)
O (OD)
I
O
I/O (OD)
* See BYTESWAP description
** The CD2481 will drive DTACK* even though the device will not respond to such byte
alignment.
INTERRUPT ACKNOWLEDGE IN*: This input qualified with DS* and A[0–6] acknowledges
CD2481 interrupts.
INTERRUPT ACKNOWLEDGE OUT*: This output is driven low during interrupt acknowledge
cycles for which no internal interrupt is valid.
INTERRUPT REQUEST* [1–3]: These outputs signal that the CD2481 has a valid interrupt for
modem-lead activity (IREQ*[1]), transmit activity (IREQ*[2]), or receive activity (IREQ*[3]).
BUS REQUEST*: This output is used to signal to the (open-drain) host processor or bus arbiter
that bus mastership is required by the CD2481.
BUS GRANT IN*: This input indicates that the bus is available after the current bus master
relinquishes the bus.
BUS GRANT OUT*: This output is asserted when BGIN* is low and no internal bus request has
been made. A daisy-chain scheme of bus arbitration can be formed by connecting BGOUT* to
BGIN* of the next device in the chain. If a priority scheme is preferred, bus requests must be
prioritized externally and bus grant routed to the BGIN* of the appropriate device.
BUS GRANT ACKNOWLEDGE*: As an input, this signal is used to determine if another
alternate bus master is in control of the bus. As an output, it signals to other bus masters that
this device is in control of the bus.
Datasheet
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