CD2481 Datasheet, PDF (42/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
Table 2. Transmit and Receive Interrupt Service Requests
Interrupt Cause
Receive Good Data ¹
Break detect
Framing error
Parity error
Receive time-out, no data
Special character match
Transmitter empty
Tx FIFO threshold ^a
Receive overrun
Clear detect
CRC error
Residual bit count
Receive abort
End of frame
Transmit underrun
Bus error ²
End of buffer ^b
1.Non-DMA mode
2.DMA mode only
Async
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HDLC
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Bisync
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X.21
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PPP
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SLIP
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MNP4^
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5.2.4
Hardware Signals and IACK Cycles
The IACK (interrupt acknowledge) bus cycle begins with the IACKIN* (Interrupt Acknowledge
In) and DS* asserted, and a value matching the appropriate PILR contents on the least-significant
seven address bus bits, A[6:0]. If the IACK cycle is valid (that is, the A[6:0] and PILR values
match), the corresponding vector from the interrupting channels LIVR is driven onto the data bus
and DTACK* asserted. DTACK* is released after DS* is removed.
Figure 4 shows the interrupt acknowledge cycle timing. It is similar to the basic host read cycle
except that IACKIN* is active, and CS* is inactive.
The three IREQn* pins are open-drain outputs requiring external pull-up resistors, nominally 4.7
kΩ. The IACKOUT* (Interrupt Acknowledge Out) is used to form a daisy-chain in systems with
more than one CD2481.
5.2.4.1
Programming the PILR Registers
The three PILRs must be programmed with values that correspond to the least-significant seven
address bits that will be present on A[6:0] during the interrupt acknowledge bus cycle. Some CPUs
output the priority level of the interrupt that is being acknowledged on the bus during the IACK
cycle. In these systems the three PILR values are unique. In other systems that do not use this
scheme, the PILR values can be the same or different depending on the specific design. When all of
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Datasheet