CD2481 Datasheet, PDF (114/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
9.2.2
chmd3
0
0
1
chmd2
1
1
0
chmd1
1
1
0
chmd0
0
1
0
Protocol
MNP4/ARAP
Reserved
Programmable Sync
Channel Option Register 1 (COR1)
COR1 – HDLC Mode (Not used in PPP mode)
Register Name: COR1
Register Description: Channel Option Register 1
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
AFLO
ClrDet
AdMd1
AdMd0
Bit 3
Flag3
Intel Hex Address: x’13
Motorola Hex Address: x’10
Bit 2
Flag2
Bit 1
Flag1
Bit 0
Flag0
If any options specified in this register are changed, an initialize command must be given to
CD2481 through the Channel Command register.
Bit 7
Address field length option
0 = Address field is 1 octet in length
1 = Address field is 2 octets in length
Bit 6
Clear detect for X.21 data transfer phase
0 = Clear detect disabled
1 = Clear detect enabled
A clear is defined as two consecutive all zero receive characters with the CTS* pin
high.
Bits 5:4
Addressing modes
00 = no address recognition
01 = 4 * 1 byte
10 = 2 * 2 byte
If this bit is set, RFAR1, RFAR2, RFAR3, and RFAR4 should contain the address
to be matched. If AFLO is set to ‘1’, an address match is made against the RFAR1
and RFAR2 pair or the RFAR3 and RFAR4 pair.
Bits 3:0
Inter-frame flag option
Defines the minimum number of flags transmitted before a frame is started.
Flag 3
0
0
1
Flag 2
Flag 1
0
0
0
0
through
1
1
Flag 0
0
1
1
minimum of 1 opening flag, with
shared closing/opening flags
permitted
minimum number of opening flags
sent
114
Datasheet