CD2481 Datasheet, PDF (161/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
Bit 1
Tx Mpty
Transmitter empty. If enabled, a group 2 interrupt is generated when the channel is
completely empty of transmit data.
Bit 0
Tx Data
Any transmit exception or transmit FIFO threshold reached in Interrupt Transfer
mode. Group 2 interrupts are generated at the end of transmit DMA buffers or when
the FIFO threshold is reached in Interrupt Transfer mode.
IER –Async-HDLC/PPP Mode
Register Name: IER
Register Description: Interrupt Enable Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Mdm
0
0
0
Bit 3
RxD
Intel Hex Address: x’12
Motorola Hex Address: x’11
Bit 2
Bit 1
Bit 0
TIMER
TxMpty
TxD
Bit 7
Bit 6:4
Bit 3
Bit 2
Bit 1
Bit 0
Modem pin change detect
Master interrupt enable for modem change detect functions. The host can select
which modem pins are watched for input change and select either or both directions
of change by programming the change detect option bits in COR4 and COR5. A
group1 type interrupt (see LIVR description) is generated from this enable.
Reserved – must be zero.
Rx data
The receive FIFO threshold has been reached in Interrupt Transfer mode, causing a
group 3 receive data interrupt. Any receive exception causes a group 3 receive
exception interrupt.
Timer
General timer(s) time-out
In Synchronous mode, this bit enables a group 1 interrupt when either timer reaches
zero.
Tx Mpty
Transmitter empty. If enabled, a group 2 interrupt is generated when the channel is
completely empty of transmit data.
Tx Data
Any transmit exception or transmit FIFO threshold reached in Interrupt Transfer
mode. Group 2 interrupts are generated at the end of transmit DMA buffers or when
the FIFO threshold is reached in Interrupt Transfer mode.
Datasheet
161