CD2481 Datasheet, PDF (45/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
5.3.4
5.3.5
5.3.6
5.4
Each channel has two timers, one 16-bit general timer 1 (GT1) and one 8-bit general timer 2 (GT2).
Their operation and programming are different in synchronous and asynchronous protocols.
Timers in Synchronous Protocols
In synchronous protocols, the timers have no special significance for the CD2481; they are
available to support the protocols. They are started by host commands or by interrupts generated by
the CD2481. General timers 1 and 2 can be started in either of two ways:
1. By loading a new value to GT1 or GT2 when the timer is not running.
2. By setting the SetTm1 or SetTm2 bits in the End of Interrupt register when terminating an
interrupt service routine. In this case, the value should be written to the appropriate Interrupt
Status register (RISR, TISR, MISR).
These timers can be disabled by a command through the CCR (Channel Command register).
Timers in Asynchronous Protocols
The receive timer is restarted from the value programmed in RTPR every time a character is
received and loaded into the FIFO, or data is read by the host. For example, receive FIFO threshold
is set to eight, and six characters are stored in the receive FIFO. If no more characters are received
and the receiver timer times-out, a receive interrupt is asserted (in DMA mode, DMA transfer
occurs). The host is expected to retrieve all six characters from the receive FIFO. Assuming the
host is still enabling this feature (that is, RET bit from the IER register bit 5 is still set), and if there
is no character being received and receiver timer times-out, a receive exception time-out interrupt
(a group 3 interrupt) is asserted. The timer can be disabled if the value in RTPR is set to ‘0’ or the
RET bit is cleared.
Transmit Timer
The TTR (Transmit Timer register) is used only if the embedded transmit command is enabled in
the COR2 register. The delay transmit command specifies the delay period loaded in the TTR; no
further transmit operations are performed until this timer reaches zero. The current state of the line
is held at either ‘0’ for send break or ‘1’ for inter-character fill.
DMA Operation
The CD2481 uses a simple, but powerful, double-buffering method that is readily compatible with
higher-level buffer control procedures, such as circular queues, link lists, and buffer pools. Each
transmitter and each receiver is assigned an ‘A’ and a ‘B’ buffer. When transmitting, the host
processor alternately fills the A and B buffers and commands the CD2481 to transmit the buffers
one at a time. When receiving, the CD2481 fills the A and B buffers and informs the host processor
when each is ready.
A simple Ownership Status bit is used for each buffer; this ensures that there are no deadlocks
between the host and the CD2481 regarding the use of a particular buffer.
Datasheet
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