CD2481 Datasheet, PDF (170/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
Bit 2
FE – Framing error
The FE bit indicates that a character has been received with an incorrect Stop bit. The
stop bit was ‘0’; it should have been ‘1’.
Bit 1
Reserved; returns ‘0’ when read.
Bit 0
Break – Break detection
The Break bit indicates that a break has been received. A break is a continuous
sequence of at least ten ‘0’ bits.
NOTES:
1. During an interrupt service routine, the host can use this register to provide a timer value as
detailed in the Receive End of Interrupt register. The host can only load one of the two timers
in the interrupt service routine.
2. 0E, FE, and break are cumulative over the entire packet in PPP mode. This means that the
respective error occurred somewhere in the packet, but did not cause an immediate interrupt.
3. The table to the right defines the encoding of RxABT and FE for an aborted receive frame:
RxABT
0
0
1
1
FE
Error
0 None
1 Not Used
0 Received abort sequence: x’7D, x”7E
1 Framing Error caused a frame abort
RISRl – SLIP/MNP4 Mode
Register Name: RISRl
Register Description: Receive Interrupt Status Register - Low
Default Value: x’00
Access: Byte Read Only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
EOF
RxAbt
0
OE
Intel Hex Address: x’8A
Motorola Hex Address: x’89
Bit 2
FE
Bit 1
0
Bit 0
Break
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Binary Value for Timer
Bit 2
Bit 1
Bit 0
If RxData in IER is set, these interrupts are enabled.
Bit 7
Reserved; returns ‘0’ when read.
Bit 6
EOF – End of frame
The EOF bit indicates that a valid end of frame (7E) character has been received, and
the 7E was not preceded by a 7D.
170
Datasheet