CD2481 Datasheet, PDF (67/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
Table 9. Data Clock Selection Using External Clock
Bit Rate
50
110
150
300
600
1200
2481
3600
4800
7200
9600
19200
38400
56000
64000
76800
115200
128000
External Clock Frequency
Clock = 35 MHz
9.765 kHz
9.765 kHz
9.765 kHz
39.062 kHz
39.062 kHz
156.250 kHz
156.250 kHz
625.00 kHz
625.00 kHz
1.250 MHz
1.250 MHz
1.250 MHz
1.250 MHz
1.250 MHz
1.250 MHz
1.250 MHz
2.00 MHz
2.00 MHz
Divisor (hex)
C2
57
40
81
40
81
40
EF
81
AC
81
40
1F
15
12
0F
10
0F
5.6
Hardware Configurations
To demultiplex the A/D[0–15] bus into separate address and data buses, external buffers and
latches are required. To reduce external circuitry, these external devices can be shared in multi–
CD2481 applications. The common control lines (ADLD*, AEN*, DATDIR*, DATEN*) to the
external devices are wire-OR’ed together. These pins are tristate, not open collector, but an external
pull-up resistor (2.2K–5.0K) must be connected to each line to ensure a logic ‘1’ when no CD2481
is a bus master.
When no higher-priority alternate bus masters are present, a daisy-chain priority scheme can be
implemented by wire OR’ing the BR* and BGACK* and connecting directly to the 680X0. The
680X0 BG* signal is then connected to the first device in the chain and daisy-chained to the
remaining devices. A lower priority bus master can then be connected at the end of the chain.
If a higher priority bus master is present, the BG* signal must be qualified before being passed into
the highest priority CD2481. If a priority encoded scheme is required, the BR* signals must be
prioritized externally and BG* signals routed to individual devices.
Datasheet
67