CD2481 Datasheet, PDF (205/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
10.6
AC Electrical Characteristics (Revisions B and D at 60 MHz)
Symbol
Parameter (Sheet 1 of 2)
t_PERIOD
t_LOW
t_HIGH
t₁
t₂
Bus Arbitration
Period of CLK input (60 MHz maximum)
CLK low phase (60/40 duty cycle, worst case)
CLK high phase (60/40 duty cycle, worst case)
CLK high to BUSCLK high
CLK high to BUSCLK low
t₁₁
t₁₂
t₁₃
t₁₄
t₁₅
t₁₆
t₁₇
t₁₈
t₁₉
t₂₀
DMA Read
CLK high to BGACK* tristate
BGIN* low to address valid ¹
Address hold after CLK high
CLK high to address tristate
CLK high to ADLD* low
CLK high to ADLD* high
Address setup to ADLD* high
CLK high to AEN*/DATEN*/DATDIR* high
CLK high to AEN*/DATEN*/DATDIR* tristate
CLK high to AEN*/DATEN*/DATDIR* low
t₂₁
t₂₂
t₂₃
t₂₄
t₂₅
t₂₆
t₂₇
t₂₈
t₂₉
DMA Write
Data setup to CLK high
Data hold after CLK high
CLK high to address valid
CLK low to AS* low
CLK high to AS* high
CLK low to DS* low
CLK high to DS* high
DTACK* low setup to CLK high
DTACK* high setup to CLK high (to avoid false termination)
t₃₁
t₃₂
t₃₃
t₃₄
t₃₅
t₃₆
Host Read/Write
CLK high to data valid
Data hold after CLK high
CLK low to DS* low
CLK high to DS* high
DTACK* low setup to CLK high
DTACK* high setup to CLK high (to avoid false termination)
t₄₁
DS* and CS* low setup to CLK high
Datasheet
MIN
16.667
6.667
6.667
0
15
2
12
10
30
0
10
30
7
MAX
10
10
17
17
25
40
20
13
16
20
20
25
27
16
15
16
15
40
16
15
205