CD2481 Datasheet, PDF (102/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
Several options are available for handling the EOF character(s). The Append bits (COR3[1:0])
select whether or not the EOF character will be included in the frame data given to the host and,
optionally, additional characters following the EOF can also be included.
If Append1 and Append0 are both ‘0’, the EOF is not given to the host. If Append1 is ‘0’ and
Append0 is ‘1’, the EOF character is included in the frame data.
Optionally, the first one or two characters following the EOF can also be included in the frame
data. If Append1 is ‘1’ and Append0 is ‘0’, the first character following EOF is given to the host;
Append1 and Append0 both set to ‘1’ cause the CD2481 to give the host the two characters
following EOF.
Note:
SYN-hunt for the next frame does not begin until after the programmed number of append
characters have been received. Thus, if SYN1 of the next frame immediately follows EOF and
Append mode selects that the first character following EOF is to be included in the previous frame
data, the device will not sync to the next frame.
Once the EOF has been received, the CD2481 will generate an End-of-Frame interrupt in either
interrupt or DMA modes. Any FCS verification must be performed by host software.
7.10
Non-8-Bit Data Transfers
In Asynchronous and programmable sync modes, it is possible to transmit and receive less than 8
bits per character. There can be 5, 6, 7, or 8 bits per character.
For HDLC mode, 8 bits per character are always transmitted. The CD2481 transmits only byte-
aligned frames. The CD2481 receives HDLC frames using transfers of 8 bits per character, except
for the last character received before the FCS. If this last character is not aligned to an 8-bit
boundary, the ResInd (residual indication) bit is set along with the EOF bit in RISRl. The residual
character is zero filled and LSB aligned in the FIFO.
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Datasheet