CD2481 Datasheet, PDF (60/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
The transfer that failed to the first buffer due to the bus error is still in the receive FIFO and is
transferred to the next buffer following the end of interrupt.
To retry the buffer from the failure point, the CPU should set the 2481OWN bit in the A/BRBSTS
register; the CPU should not set the TermBuff bit when writing to REOIR at the end of the
interrupt. This causes the last transfer to be retried; should a bus error occur again, the above
procedure is repeated. The CPU should check to ensure that a bad location is not continually
retried.
5.5
Bit Rate Generation and Data Encoding
BRG and DPLL Operation
Data clocks are generated in the CD2481 by feeding one of a number of clock sources into a
programmable divider. The clock source and divisor are programmable separately for each channel
and direction by the user. Clock options are programmed in the Transmit Clock Option register and
the Receive Clock Option register. The divisors are programmed in the Transmit Bit Rate Period
register and the Receive Bit Rate Period register. The possible clock sources are:
Transmit
1. Clk 0 – CLK input/8
2. Clk 1 – CLK input/32
3. Clk 2 – CLK input/128
4. Clk 3 – CLK input/512
5. Clk 4 – CLK input/2048
6. TXCLK pin
7. Receive bit clock
Receive
1. Clk 0 – CLK input/8
2. Clk 1 – CLK input/32
3. Clk 2 – CLK input/128
4. Clk 3 – CLK input/512
5. Clk 4 – CLK input/2048
6. RXCLK pin
The CLK input is nominally 35 MHz.
The divisor can be programmed for values from 1–255. To maximize the accuracy of edge
detection in Asynchronous and DPLL modes, the highest frequency clock and largest divisor
combination should be selected.
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Datasheet