CD2481 Datasheet, PDF (117/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
Bit 6
FCS append
0 = Receive CRC is not passed to the host at end of frame
1 = Receive CRC is passed to the host at end of frame
Bit 5
Reserved – must be zero.
Bit 4
CRCNinv
0 = CRC is transmitted inverted (that is, CRC V.41)
1 = CRC is not transmitted inverted (that is, CRC-16)
Bit 3
Reserved – must be zero.
Bit 2
RTS automatic output enable
When set, if the channel is enabled, the CD2481 automatically asserts the RTS* out-
put when it has characters to send. When Idle-in Mark mode is selected, RTS* is
asserted prior to opening flags and remains asserted until after a closing flag has been
transmitted.
Bit 1
CTS automatic enable
Enables CTS* input to be used as automatic transmitter enable/disable. If enabled,
the CTS input is checked before frame transmission is started.
Bit 0
DSR Automatic Enable
Enable the DSR* input as automatic receiver enable/disable. If enabled, the pin is
checked at the beginning of each received frame.
COR2 – Bisynchronous Mode
Register Name: COR2
Register Description: Channel Option Register 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
LRC
BCC
EBCDIC
CRCNinv
Bit 3
NoStrip
Intel Hex Address: x’14
Motorola Hex Address: x’17
Bit 2
Alt–Ctrl
Bit 1
SYN1
Bit 0
SYN0
Bit 7
Longitudinal redundancy check
0 = CRC16 used for BCC
1 = LRC used for BCC
Bit 6
BCC Append
0 = Receive BCC is not passed to the host at end of frame.
1 = Receive BCC is passed to the host at end of frame.
Bit 5
EBCDIC
0 = ASCII character set in use.
1 = EBCDIC character set in use.
Bit 4
CRCNinv
0 = CRC is transmitted inverted (CRC V.41).
1 = CRC is not transmitted inverted (CRC-16).
Datasheet
117