CD2481 Datasheet, PDF (77/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
Indication (0, off) from the remote. If detected, the remainder of the current frame will be
discarded, and a clear detect indication will be passed to the CPU via the RISR. However, the
channel remains in HDLC mode until modified by the CPU.
7.2
PPP (Point-to-Point Protocol) Mode
7.2.1
Character Format
PPP uses the async-HDLC character format, which is fixed as one start bit, eight data bits, one stop
bit. There is no parity bit. The character format is as shown in Figure 15.
Using the bit definitions from the standard format (Figure 15), the data bits are identified as D1–
D8. D1 is the LSB. Characters are identified as either bits (D1–D8) or as hexadecimal values
showing the hex value for bits D5–D8 first, followed by the hex value for D1–D4. Thus, a flag
character is 01111110, and is indicated as a hex 7E. A control-escape character is 10111110, or 7D.
Figure 15. Character Format
START D1 D2
D3
D4
D5
D6
D7
D8 STOP
The line is high prior to the Start
bit. The high value is either due
to a line idle or the Stop bit from
the previous character.
The Start bit of the next
character could begin no earlier
than immediately after the
previous Stop bit.
7.2.2
Frame Format
The standard frame format is as follows:
Figure 16. Point-to-Point Protocol Frame
FLAG A-FIELD C-FIELD FRAME DATA CHARACTERS FCS-1 FCS-2 FLAG Interframe idle time fill
or next address.
The closing flag (7E) of the previous frame may be the same
flag used as the opening of the next frame. This is a shared
flag.
7.2.3
A and C fields
The chip passes the A and C fields to and from the host. The chip does not perform any special
processing on these fields.
FCS (Frame Check Sequence)
PPP mode uses the same 16-bit CRC as standard HDLC mode (V.41).
Datasheet
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