CD2481 Datasheet, PDF (172/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
9.5.2.5
Bit 5
Bit 4
Bit 3
Bits 2:0
The end of a receive buffer has been reached. Used only for DMA supported trans-
mission. The end of one of the host-supplied receive buffers has been reached.
Reserved; returns ‘0’ when read.
Status during buffer A or buffer B data transfer
0 = Buffer A
1 = Buffer B
Reserved; returns ‘0’ when read.
Receive FIFO Output Count (RFOC)
Register Name: RFOC
Register Description: Receive FIFO Output Count Register
Default Value: x’00
Access: Byte Read Only
Bit 7
Bit 6
Bit 5
Bit 4
0
0
0
RxCt4
Bit 3
RxCt3
Intel Hex Address: x’33
Motorola Hex Address: x’30
Bit 2
RxCt2
Bit 1
RxCt1
Bit 0
RxCt0
9.5.2.6
Bits 7:5
Bits 4:0
Reserved; returns ‘0’ when read.
Receive data count
If the receive channel is interrupt driven, a non-zero value in this bit field is the num-
ber of data characters available for transfer within the current receive interrupt.
Receive Data Register (RDR)
Register Name: RDR
Register Description: Receive Data Register
Default Value: x’00
Access: Byte Read Only
Bit 7
Bit 6
Bit 5
D7
D6
D5
Bit 4
D4
Bit 3
D3
Intel Hex Address: x’F8
Motorola Hex Address: x’F8
Bit 2
D2
Bit 1
D1
Bit 0
D0
This Virtual register accesses the receive data FIFO of a channel interrupting for receive data
transfer. This register address is used for all channels to transfer receive FIFO data to the host, if
programmed in Interrupt Transfer mode. Data must be read as bytes, and follows the rules listed in
Section 9.3 for the positioning of valid data on the bus. If the BYTESWAP pin is high, data is valid
on A/D[0–7], if BYTESWAP is low, data is valid on A/D[8–15]. This is true because the RDR is on
an even address.
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Datasheet