CD2481 Datasheet, PDF (213/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
Figure 28. DMA Read Cycle Timing
CLK
BUSCLK
t₂₄
AS*
t₂₆
DS*
t₂₃
A[0–7]
A/D[0–15]
DTACK*
BERR*
t₂₅
t₂₇
t₂₂
t₂₁
t₂₉
t₂₈
t_S
t_H
BERR* Timing:
t_S = setup time to CLK rising edge = 10 ns
t_H = hold time after CLK rising edge = 20 ns
Datasheet
213