CD2481 Datasheet, PDF (176/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
9.5.3.3
Bit 4
Bits 3:2
Bit 1:0
Ten
Tact
Teoi
Sequence of Events
0
0
1
0
1
1
0
1
0
0
0
Idle
0
Transmit interrupt requested, but not
asserted
0
Transmit interrupt asserted
0
Transmit interrupt acknowledged
1
Transmit interrupt service routine
completed
Unused; returns ‘0’ when read.
Tvct [1:0]
Transmit Vector bits are set by the CD2481 to provide the lower two bits of the vec-
tor supplied to the host CPU during an interrupt acknowledge cycle. Transmit vector
is decoded as follows: Tvct [1] = 1, and Tvct [0] = 0.
Tcn [1:0]
Transmit channel number is set by the CD2481 to indicate the channel requiring
transmit interrupt service.
Transmit Interrupt Status Register (TISR)
Register Name: TISR
Register Description: Transmit Interrupt Status Register
Default Value: x’00
Access: Byte Read Only
Bit 7
Bit 6
Bit 5
Bit 4
Berr
EOF
EOB
UE
Bit 3
BA/BB
Intel Hex Address: x’89
Motorola Hex Address: x’8A
Bit 2
0
Bit 1
TxEmpty
Bit 0
TxDat
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Binary Value for Timer
Bit 2
Bit 1
Bit 0
When the host receives a transmit interrupt, the following status is provided in this register:
Bit 7
Berr – Bus error (written by the CD2481)
0 = no bus error
1 = bus error was detected on the last transfer
Bit 6
EOF – Transmit end of frame indication in the DMA mode
This interrupt occurs when the final data character of a transmit frame is transferred
to the transmit FIFO.
Bit 5
EOB – Transmit end of buffer indication in the DMA mode
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Datasheet