CD2481 Datasheet, PDF (162/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
9.5.1.3
Local Interrupting Channel Register (LICR)
Register Name: LICR
Register Description: Local Interrupting Channel Register
Default Value: C1:C0 contain channel number
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
X
X
X
X
Bit 3
C1
Intel Hex Address: x’25
Motorola Hex Address: x’26
Bit 2
C0
Bit 1
X
Bit 0
X
9.5.1.4
These per-channel registers are initialized with each channel number. The locations are RAM
registers and can be used for any purpose.
Bits 7:4
User-defined
Bits 3:2
Defines the interrupting channel number
C1
C0
0
0
0
1
1
0
1
1
Bits 1:0
User-defined
Interrupt Stack Register (STK)
Channel Number
Channel 0
Channel 1
Channel 2
Channel 3
Register Name: STK
Register Description: Interrupt Stack Register
Default Value: x’00
Access: Byte Read Only
Bit 7
Bit 6
Bit 5
Bit 4
CLvl [1]
MLvl [1]
TLvl [1]
0
Bit 3
0
Intel Hex Address: x’E0
Motorola Hex Address: x’E2
Bit 2
TLvl [0]
Bit 1
MLvl [0]
Bit 0
CLvl [0]
This register is a 4-bit-deep by 2-bit-wide stack that holds the internal interrupt nesting history. The
stack is pushed from bits 7 and 0 towards the center during an interrupt acknowledge cycle and
popped from the center during a write to an end of interrupt register.
Bits 7, 0
CLvl [0:1]These bits provide the currently active interrupt level.
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Datasheet