CD2481 Datasheet, PDF (62/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
Figure 10. Bit Rate Generator/DPLL
Period Register
(RBPR or TBPR)
System
Clock
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
clk 0
clk 1
clk 2
clk 3
clk 4
RXCin or TXCin
RX bit clk
(for TX BRG only)
Adjustments
applied here
(for DPLL only)
0
1
2
3
4 Mux
5
6
7
Mux
Count Register
(RBCR or TBCR)
dec/inc ÷ N
Zero Detect
From RCOR/TCOR
Receive Clock Option Register (RCOR)
TLVal
0
dpllEn
Dpllmd1
Dpllmd0
-
ClkSel2
Transmit Clock Option Register (TCOR)
ClkSel1
ClkSel0
0
Ext-1X
CA C8 B R/W
ClkSel2
ClkSel1
ClkSel0
C2 C0 B R/W
0
LLM
0
Table 4. Clock Source Select (Sheet 1 of 2)
ClkSel2
0
0
0
0
1
1
ClkSel1
0
0
1
1
0
0
ClkSel0
0
1
0
1
0
1
Select
Clk 0
Clk 1
Clk 2
Clk 3
Clk 4
Reserved
62
Datasheet