CD2481 Datasheet, PDF (122/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
COR2 – MNP4/SLIP Mode
Register Name: COR2
Register Description: Channel Option Register 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
0
0
0
0
Bit 3
RLM
Intel Hex Address: x’14
Motorola Hex Address: x’17
Bit 2
RtsAO
Bit 1
CtsAE
Bit 0
DsrAE
Note: SLIP, MNP4, and Automatic In-Band Flow Control modes are only available on Revision B and
later devices.
Bits 7:6
Reserved – must be zero. No in-band flow control in MNP4 mode.
Bits 5:4
Reserved – must be zero.
Bit 3
RLM – Remote Loop Back mode
RLM = 1 enables Remote Loopback mode
RLM = 0 disables Remote Loopback mode
Bit 2
RtsAO – RTS automatic output enable
If RtsAO = 1, then the RTS* output pin remains enabled during DMA or character
bursts from the transmit FIFO. If the CTS* input pin goes high, then RTS* goes high
and transmission is stopped after the current burst is completed.
Bit 1
CtsAE – CTS automatic enable
When clear, the transmitter output enable is independent of the CTS* input pin.
When set, the CTS* input pin is evaluated prior to the transmission of each character.
If CTS* is asserted low, that character is transmitted completely. If CTS* is high,
that character transmission is held until CTS* goes low.
Bit 0
DsrAE – DSR automatic enable
When clear, the receiver input enable is independent of the DSR* input pin.
When set, the DSR* input pin is evaluated at the end of each received character. If
DSR* is asserted low, the receiver input is enabled for the next character. If DSR*
is high, the receiver is disabled until DSR* goes low.
COR2 – Programmable Sync Mode
Register Name: COR2
Register Description: Channel Option Register 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
SYN2
Strip
0
0
Bit 3
0
Intel Hex Address: x’14
Motorola Hex Address: x’17
Bit 2
RtsAO
Bit 1
CtsAE
Bit 0
DsrAE
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Datasheet