CD2481 Datasheet, PDF (165/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
9.5.2.3
Receive Interrupt Status Register (RISR
Register Name: RISR
Register Description: Receive Interrupt Status Register
Default Value: x’00
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
RISR High
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
RISR Low
Intel Hex Address: x’8A
Motorola Hex Address: x’88
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
This register reports the status of the channel during the receive interrupt service. It is a 16-bit
register, with the lower byte displaying current receive character oriented status while the upper
byte displays current DMA interrupt status. The upper byte is not used if DMA mode is not active.
Note: During an interrupt service routine, the host can use this register to provide a timer value as
detailed in the Receive End of Interrupt register. The host can only load ne of the two timers in the
interrupt service routine.
RISRl – HDLC Mode
Register Name: RISRl
Register Description: Receive Interrupt Status Register - Low
Default Value: x’00
Access: Byte Read Only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
EOF
RxAbt
CRC
OE
Intel Hex Address: x’8A
Motorola Hex Address: x’89
Bit 2
Reslnd
Bit 1
0
Bit 0
ClrDct
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Binary Value for Timer
Bit 2
Bit 1
Bit 0
If RxData in IER is set, these interrupts are enabled.
Bit 7
Reserved – returns ‘0’ when read.
Bit 6
Receiving a data frame is essentially complete.
Bit 5
Received abort sequence terminating the frame.
Bit 4
CRC error on current frame.
Datasheet
165