CD2481 Datasheet, PDF (65/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
Table 8. Bit Rate Constants, CLK = 60 MHz (Sheet 2 of 2)
Bit Rate
3600
4800
7200
9600
19200
38400
56000
57600
64000
76800
115200
128000
134400
150000
230400
Divisor
81
61
40
40
81
40
2c
81
26
61
40
3a
37
31
20
Clock
clk2
clk2
clk2
clk1
clk0
clk0
clk0
clk0
clk0
clk0
clk0
clk0
clk0
clk0
clk0
Error
0.16%
0.35%
0.16%
0.16%
0.35%
0.16%
0.05%
0.16%
0.16%
0.35%
0.16%
0.69%
0.35%
0.00%
1.38%
Transmit and receive data can be encoded and decoded in NRZ, NRZI, or Manchester formats. For
NRZI, at the start of transmission, a learning data stream of contiguous zeros achieves bit
synchronization; for Manchester, an alternating pattern of ones and zeros is required.
NRZ, NRZI, and Manchester — Data encoding schemes used in various synchronous protocols. In
NRZ, the signal condition represents the data type, high for a logic 1 and low for a logic 0. In NRZ
and NRZI type of encoding, the transitions of the data stream occur at the beginning of the bit cell.
In NRZI, the signal condition switches to the opposite state to send a binary 0. In Manchester
encoding, the transitions are always in the middle of the bit cell. A high-to-low transition is made
to send a logic 1, and a low-to-high transition to send a logic 0. The following timing diagrams
illustrate the encoding method. The data bits are 0110010.
Example 3
This example illustrates programming the Digital Phase locked loop at 128 kbps in NRZI mode
using the internal clock, at a system clock frequency of 35 MHz.
Divisor loaded into R/TBPR = 33 or 21h
Value loaded into RCOR = 28h, to enable the DPLL, NRZI framing and select clk0.
Example 4
This example illustrates programming the Digital Phase locked loop in the ×1 External Clock
mode, with Manchester encoding.
Divisor loaded into RBPR = 01h, to enable ×1 external clock
Value loaded into RCOR = 36h, to enable the DPLL, select Manchester framing, and external
clock.
Datasheet
65