CD2481 Datasheet, PDF (187/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
9.6.4.8
B Receive Buffer Status (BRBSTS)
Register Name: BRBSTS
Register Description: Receive Buffer ‘B’ Status
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Berr
EOF
EOB
0
Bit 3
0
Intel Hex Address: x’4D
Motorola Hex Address: x’4E
Bit 2
0
Bit 1
0
Bit 0
2481own
These registers contain the current status of associated receive buffers and enable the buffers to be
passed between the host and CD2481. Status bits are defined as follows:
Bit 7
Bus error (set by the CD2481 and cleared by the host CPU)
0 = No bus error
1 = Bus error occurred on the last transfer; the suspect address is available in
RCBADR.
Bit 6
End of frame (set by the CD2481 and cleared by the host CPU); sync modes only.
0 = This buffer does not terminate a frame.
1 = This buffer terminates a frame.
Bit 5
Buffer complete (set by the CD2481 and cleared by the host CPU)
0 = Buffer not complete.
1 = Buffer complete.
Bits 4:1
Reserved – must be zero.
Bit 0
Ownership of the transfer buffer (set by the host CPU and cleared by the CD2481)
0 = Buffer not free to be used by CD2481.
1 = Buffer free to be used by CD2481.
When the Buffer Completed bit is set by the CD2481, the buffer is free for the host to process.
(RBCNT information is updated to the number of bytes available in the buffer, and a new buffer
can be allocated.)
Datasheet
187