CD2481 Datasheet, PDF (219/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

DMA 45
DPLL 60
FIFO and timer 44
receive FIFO 44
transmit FIFO 44
ordering information example 216
P
package specifications 215
Parity mode 115
pin descriptions 16
pin diagram 15
pin functions 16
PPP mode 120
Programmable Sync 100
Programmable Sync Mode 122, 135, 136
programming the PILR registers 42
Protocol mode 113
protocol processing 75
R
read cycle, host 38
receive buffer interrupts 58
receive bus errors 59
receive DMA transfer 53
receive FIFO operation 44
receive time-out 59
Receive Transfer mode 113
receiver
A and B buffers 53
fixed operations 80
options 80
register definitions 25
register descriptions, detailed 112
register table 20
registers
Bit Rate and Clock Option registers
RBPR 22, 29, 145
RCOR 22, 29, 145
TBPR 22, 29, 146
TCOR 22, 29, 147
Channel Command and Status registers
Datasheet
CCR 22, 29, 148
CSR 22, 30, 153
MSVR-DTR 22, 31, 158
MSVR-RTS 22, 31, 158
STCR 22, 30, 150
DMA Receive registers
ARBADRL 24, 34, 184
ARBADRU 24, 34, 184
ARBCNT 24, 34, 186
ARBSTS 24, 34, 186
BRBADRL 24, 34, 185
BRBADRU 24, 34, 185
BRBCNT 24, 34, 186
BRBSTS 24, 34, 187
RCBADRL 24, 34, 188
RCBADRU 24, 34, 188
DMA registers
BERCNT 24, 34, 182
DMABSTS 24, 34, 183
DMR 24, 34, 182
DMA Transmit registers
ATBADRL 24, 34, 189
ATBADRU 24, 34, 189
ATBCNT 24, 35, 191
ATBSTS 24, 35, 191, 193, 194, 195
BTBADRL 24, 35, 190
BTBADRU 24, 35, 190
BTBCNT 24, 35, 191
BTBSTS 24, 35, 192, 193
TCBADRL 24, 35, 196
TCBADRU 24, 35, 196
Global registers
CAR 20, 25, 112
GFRCR 20, 25, 112
Interrupt registers
IER 22, 31, 160, 161
LICR 22, 31, 162
LIVR 22, 31, 159
STK 22, 31, 162
Modem Interrupt registers
MEOIR 23, 34, 181
MIR 23, 33, 179
MISR 23, 33, 180
219