CD2481 Datasheet, PDF (211/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
Figure 26. Bus Release Timing
CLK
BUSCLK
BR*
BGIN*
ADLD*
A[0–7]
t₁₅
t₁₂
t₁₆
t₁₇
A[8–15]
t₁₃
A[0–7]
A/D[0–15]
A[16–31]
NOTE
AS*
AEN*/DATEN*/
DATDIR*
t₂₄
t₂₀
BGACK*
R/W*
NOTE: In DMA Read cycle, these pins will be tristate; in DMA Write cycle, these pins will be D[0:15].
Datasheet
211