CD2481 Datasheet, PDF (40/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
5.2.1
5.2.2
Contexts and Channels
The registers in the CD2481 are grouped into Global, Virtual, and four sets of Per-Channel
registers. The CD2481 is normally in the background context, where the CAR (Channel Access
Register) selects the channel number for Per-Channel registers. The interrupt context begins with
the interrupt acknowledge bus cycle, and ends with a write access to the appropriate End of
Interrupt register (EOIR). During the interrupt context, only the per-channel registers for the
channel number being serviced are available; the CAR has no effect. Most Global registers are
available at all times, but some are shared by the four channels, such as the FIFO registers. These
are called Virtual registers, and must be accessed only during an interrupt context.
Interrupt contexts can be nested so that a higher-priority interrupt service can preempt a lower
priority interrupt already in progress. The CD2481 pushes the current interrupt context onto the
stack, visible in the STK (Stack register), and enters the context for the newly acknowledged
interrupt. Any register accesses are in the new interrupt context until the host does a write to the
appropriate EOIR for the top-level context. The CD2481 pops the top-level context off the stack
and returns to the previous interrupt context.
Interrupt Registers
The IER (Interrupt Enable register) and the LIVR (Local Interrupt Vector register) are Per-Channel
registers. IER contains bits used to enable or disable the various interrupt sources within the
CD2481. The LIVR value is output on the data bus during the interrupt acknowledge cycle. There
are sets of three Global registers that correspond to the three types of interrupts: Receive, Transmit,
and Modem. The Priority Interrupt Level registers — RPILR, TPILR, and MPILR — are
programmed to contain the value that will be present on the address bus during the interrupt
acknowledge bus cycle for each type of interrupt. The Interrupt Status registers — RISR, TISR, or
MISR — are examined during the interrupt service routine to determine the cause of each type of
interrupt. The TDR (Transmit Data) and RDR (Receive Data) registers provide access to the FIFO
buffers for each channel. They must not be accessed outside of the appropriate interrupt context. A
write operation to the End of Interrupt registers — REOIR, TEOIR, or MEOIR — must be the last
access to the CD2481 at the end of this handler routine to return it to its non-interrupt context.
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Datasheet