CD2481 Datasheet, PDF (175/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
9.5.3
9.5.3.1
Transmit Interrupt Registers
Transmit Priority Interrupt Level Register (TPILR)
Register Name: TPILR
Register Description: Transmit Priority Interrupt Match Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
User Assigned Transmit Priority Match Value
Intel Hex Address: x’E2
Motorola Hex Address: x’E0
Bit 1
Bit 0
This register must be initialized by the host to contain the codes that are presented on the address
bus by the host system to indicate which of the three CD2481 interrupt types (modem, transmit, or
receive) is being acknowledged when IACKIN* is asserted. The CD2481 compares bits 0–6 in this
register with A[0–6] to determine if the acknowledge level is correct. The value programmed in the
MSB of the register has no effect on the IACK cycle.
The TPILR must contain the code used to acknowledge transmit interrupts.
Note: Bit 7 of this register is always read back as ‘0’. When each of the three Priority Interrupt Level
registers are programmed with the same value, they are internally prioritized, with receive as the
highest priority, followed by transmit and modem.
9.5.3.2
Transmit Interrupt Register (TIR)
Register Name: TIR
Register Description: Transmit Interrupt Register
Default Value: None, value varies
Access: Byte Read Only
Bit 7
Bit 6
Bit 5
Bit 4
Ten
Tact
Teoi
0
Intel Hex Address: x’EE
Motorola Hex Address: x’EC
Bit 3
Tvct [1]
Bit 2
Tvct [0]
Bit 1
Tcn [1]
Bit 0
Tcn [0]
Bit 7
Ten
Transmit enable is set by the CD2481 to initiate a transmit interrupt request
sequence. It is cleared during a valid transmit interrupt acknowledge cycle.
Bit 6
Tact
Transmit active is set automatically when Ten is set, and the Fair Share logic allows
the assertion of a transmit interrupt request. It is cleared when the host CPU writes
to the Transmit End of Interrupt register.
Bit 5
Teoi
Transmit end of interrupt is set automatically when the host CPU writes to the Trans-
mit End of Interrupt register while in a transmit interrupt routine.
Datasheet
175