CD2481 Datasheet, PDF (182/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
9.6
9.6.1
DMA Registers
DMA Mode Register (DMR)
Register Name: DMR
Register Description: DMA Mode Register
Default Value: x’00
Access: Byte Write Only
Bit 7
Bit 6
Bit 5
EnSync
0
0
Bit 4
0
Bit 3
ByteDMA
Intel Hex Address: x’F4
Motorola Hex Address: x’F6
Bit 2
0
Bit 1
0
Bit 0
0
9.6.2
This register is write only. No error occurs if the register is read, but the read value is not
consistent.
Bits 7
Internal DTACK synchronization enable. If external synchronization of DTACK
with BUSCLK is not provided, an internal synchronization can be enabled by setting
this bit.
Bits 6:4
Reserved – must be zero.
Bit 3
Byte DMA
0 = The CD2481 attempts to perform 16-bit data transfers whenever possible, and 8-
bit data transfers only when necessary (when only one byte is available or there are
odd address boundaries).
1 = The CD2481 always performs 8-bit DMA transfers, the position of the data on
the bus still follows the normal rules relating to the BYTESWAP pin.
Bits 2:0
Reserved – must be zero.
Bus Error Retry Count (BERCNT)
Register Name: BERCNT
Register Description: Bus Error Retry Count Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Binary Value
Intel Hex Address: x’8D
Motorola Hex Address: x’8E
Bit 2
Bit 1
Bit 0
When this register is programmed to zero, any bus error causes a receive/transmit interrupt to be
generated and DMA operations suspended on the buffer in error until the interrupt is processed by
the host CPU.
When this register contains a non-zero value and when a bus error occurs, the CD2481 decrements
the register value by one and retries the same DMA operation. If the value reaches zero, the next
bus error causes an interrupt; at that time a new count can be loaded by the host CPU. This is a
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Datasheet