CD2481 Datasheet, PDF (153/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
9.4.3
Bits 5:4
Bit 3
Bit 2
Bits 1:0
frame. All data in the FIFO following the abort is discarded. If DMA is used, the
remaining data up to the EOF is discarded.
Reserved – must be zero.
sndsp – Send special character command
When clear, the frame, XON, and XOFF bits described below have no meaning.
When set, the host should also set one of the following bits: frame, XON, or XOFF.
frame – Send framing error
Causes the next character in the transmit stream to be sent with an incorrect stop bit
(stop bit is ‘0’).
This bit is intended as a test function. Unlike the Abort bit, this bit does not terminate
the transmission.
Reserved – must be zero.
Channel Status Register (CSR)
This status register stores the current state of the channel. It can be read by the host at any time. The
states of the RxEn and the TxEn bits are controlled by host CPU commands to the CCR.
CSR – HDLC Mode
Register Name: CSR
Register Description: Channel Status Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
RxEn
RxFlag
RxFrame
RxMark
Bit 3
TxEn
Intel Hex Address: x’19
Motorola Hex Address: x’1A
Bit 2
TxFlag
Bit 1
TxFrame
Bit 0
TxMark
Bit 7
Receiver enable
0 = Receiver is disabled
1 = Receiver is enabled
Bit 6
Rx flag
0 = Currently not receiving flag/sync
1 = Currently receiving flag/sync
Bit 5
Rx frame
0 = Currently not receiving frame
1 = Currently receiving frame
Bit 4
Rx mark
0 = Currently not receiving continuous mark
1 = Currently receiving continuous mark
Bit 3
Transmitter enable
0 = Transmitter is disabled
1 = Transmitter is enabled
Datasheet
153