CD2481 Datasheet, PDF (192/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
9.6.5.8
B Transmit Buffer Status (BTBSTS) –Async Mode
Register Name: BTBSTS
Register Description: Transmit Buffer ‘B’ Status Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Berr
EOF
EOB
0
Bit 3
0
Intel Hex Address: x’5D
Motorola Hex Address: x’5E
Bit 2
0
Bit 1
INTR
Bit 0
2481own
These registers contain the status of the associated transmit buffer, and enables successive buffers
to be passed between the host and the CD2481. Status bits within the register are defined as:
Bit 7
Bus error (set by the CD2481 and cleared by the host CPU)
0 = no bus error
1 = bus error occurred on the last transfer; the suspect address is available in
TCBADR
Bit 6
End of frame (set and cleared by host CPU)
0 = this buffer is not the last in frame/block
1 = this buffer is the last in frame/block
Bit 5
End of a transmit buffer has been reached. Used only for DMA supported transfer.
The end of one of the host supplied transmit buffers has been reached. This bit is set
by the CD2481 and cleared by the host CPU.
Bit 4
Reserved – must be zero.
Bit 3
Append (Buffer A only, buffer B must be zero; set and cleared by the host CPU)
0 = no data is appended to the buffer
1 = data can be appended to buffer after Tx started
Bit 2
Reserved – must be zero.
Bit 1
Interrupt
0 = no interrupt required after the buffer is sent
1 = interrupt required after the buffer is sent
Bit 0
Ownership of the transfer buffer (set by the host CPU and cleared by the CD2481)
0 = buffer not ready to be used by the CD2481
1 = buffer is ready for the CD2481 to transmit
To start transmission of a buffer, the host must set the ATBADR/BTBADR (Transmit Buffer
Address) and ATBCNT/BTBCNT (Transmit Buffer Count) registers, and then set the 2481OWN
bit. If the CD2481 is to generate and send the CRC for the frame, the CRC bit in COR1 must be set.
If the buffer contains the end of a frame, the EOF bit must also be set. When the buffer has been
sent, the EOB bit is set by the CD2481, and 2481OWN is reset, allowing a new buffer to be
allocated.
Setting the Append bit allows data to be added to the buffer after transmission has begun. In this
mode, the host sets ATADR and ATCNT as normal, but when new data is appended to the buffer,
the ATBCNT/BTBCNT (Transmit Buffer Count) can be updated. When the A buffer is used in
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Datasheet