CD2481 Datasheet, PDF (50/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
Figure 7. Transmitter A and B Buffers
CD2481 Transmit
DMA Registers
ATBADR (32)
ATBCNT (16)
ATBSTS (8)
(Status Register)
Starting Address
Buffer Byte Count
TABADR (32) ^{Current Count}
(Currently using Buffer A)
BTBADR (32)
BTBCNT (16)
BTBSTS (8)
(Status Register)
Starting Address
Buffer Byte Count
Physical
Memory
Transmit
Buffer
A
Transmit
Buffer
B
NOTE: Number of bits in each register is shown in parentheses (). Buffer A and buffer B do not need
to be the same length.
5.4.6
Synchronous Transmitter Examples
In Figure 7, buffers A and B are contained in RAM external to the CD2481. All else (DMABSTS,
ATBADR, TCBADR, ATBCNT, ATBSTS, BTBADR, BTBCNT, and BTBSTS) is inside the
CD2481.
Example 1
Transmit a frame out of channel 1, with no chaining.
1. The host checks the Ntbuf bit in the DMABSTS register for channel 1 to determine which
buffer is next. In this example, Ntbuf is set to ‘0’ indicating that buffer A is used next.
2. The host sets up the buffer data, the starting address — ATBADR, and the buffer byte count
— ATBCNT.
3. The host then sets up the ATBSTS (‘A’ Buffer Status) register. The EOF bit is set to indicate
that there is no chaining. The 2481OWN bit is set to give ownership to the CD2481. By setting
2481OWN, the host commands the CD2481 to start transmission. Thus, everything must be
ready (starting address, buffer data, byte count) prior to setting 2481OWN.
4. The CD2481 starts frame transmission out of channel 1. When transmission is started, the
CD2481 sets Tbusy bit in DMABSTS. As transmission progresses, the current buffer pointer,
TCBADR, is updated by the CD2481. Also, at the start of transmission, the Next Buffer bit,
Ntbuf, is set to ‘1’ to notify the host that buffer B is next.
5. The CD2481 completes frame transmission by adding any necessary CRCs and trailing frame
delimiters.
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Datasheet