CD2481 Datasheet, PDF (179/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
9.5.4
9.5.4.1
Modem Interrupt Registers
Modem Priority Interrupt Level Register (MPILR)
Register Name: MPILR
Register Description: Modem Priority Interrupt Match Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
User Assigned Modem Priority Match Value
Intel Hex Address: x’E1
Motorola Hex Address: x’E3
Bit 1
Bit 0
This register must be initialized by the host to contain the codes that are presented on the address
bus by the host system to indicate which of the three CD2481 interrupt types (modem, transmit, or
receive) is being acknowledged when IACKIN* is asserted. The CD2481 compares bits 0–6 in this
register with A[0–6] to determine if the acknowledge level is correct. The value programmed in the
MSB of the register has no effect on the IACK cycle.
The MPILR must contain the code used to acknowledge modem/timer interrupts.
Note: Bit 7 of this register is always read back as ‘0’. When each of the three Priority Interrupt Level
registers is programmed with the same value, they are internally prioritized, with receive as the
highest priority, followed by transmit and modem.
9.5.4.2
Modem Interrupt Register (MIR)
Register Name: MIR
Register Description: Modem Interrupt Register
Default Value: x’00
Access: Byte Read Only
Bit 7
Bit 6
Bit 5
Bit 4
Men
Mact
Meoi
0
Intel Hex Address: x’ED
Motorola Hex Address: x’EF
Bit 3
Mvct [1]
Bit 2
Mvct [0]
Bit 1
Mcn [1]
Bit 0
Mcn [0]
Bit 7
Men
Modem enable is set by the CD2481 to initiate a modem interrupt request sequence.
It is cleared during a valid modem interrupt acknowledge cycle.
Bit 6
Mact
Modem active is set automatically when Men is set, and the Fair Share logic allows
the assertion of a modem interrupt request. It is cleared when the host CPU writes to
the Modem End of Interrupt register.
Bit 5
Meoi
Modem end of interrupt is set automatically when the host CPU writes to the Modem
End of Interrupt register while in a modem interrupt routine.
Datasheet
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