CD2481 Datasheet, PDF (180/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
9.5.4.3
Bit 4
Bits 3:2
Bit 1:0
Mact
0
1
1
0
0
Meoi
0
0
1
1
0
Sequence of
Events
0
Idle
0
Modem interrupt requested, but not
asserted
0
Modem interrupt asserted
0
Modem interrupt acknowledged
1
Modem interrupt service routine
completed
Reserved; returns ‘0’ when read.
Mvct [1:0]
Modem Vector bits are set by the CD2481 to provide the lower two bits of the vector
supplied to the host CPU during an interrupt acknowledge cycle. Modem vector is
decoded as follows: Mvct [1] = 0, and Mvct [0] = 1.
Mcn [1:0]
Modem channel number is set by the CD2481 to indicate the channel requiring
modem interrupt service.
Modem (/Timer) Interrupt Status Register (MISR)
Register Name: MISR
Register Description: Modem Interrupt Status Register
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
DSRChg
CDChg
CTSChg
Bit 3
Reserved
Intel Hex Address: x’88
Motorola Hex Address: x’8B
Bit 2
Bit 1
Timer2
Bit 0
Timer1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Binary Value for Timer
Bit 2
Bit 1
Bit 0
When the host receives a modem interrupt, the following status is provided in this register:
Bit 7
DSR changed
A logic ‘1’ indicates that a change has been detected on the DSR* input. The change
detect is programmed in COR4 and COR5.
Bit 6
CD changed
A logic ‘1’ indicates that a change has been detected on the CD* input. The change
detect is programmed in COR4 and COR5.
180
Datasheet