CD2481 Datasheet, PDF (120/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

CD2481 — Programmable Four-Channel Communications Controller
COR2 – X.21 Mode
Register Name: COR2
Register Description: Channel Option Register 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
0
0
ETC
0
Bit 3
0
Intel Hex Address: x’14
Motorola Hex Address: x’17
Bit 2
0
Bit 1
0
Bit 0
0
Bits 7:6
Bit 5
Bit 4:0
Reserved – must be zero.
Embedded transmitter command enable
If set, embedded command in the FIFO is detected and acted upon.
Reserved – must be zero.
FIFO Data Sequence to Implement the Embedded Transmit Command
In X.21 mode, this feature is provided to simplify the transmission of both repetitive data and data
synchronized to the ‘C’ lead. The command is a sequence of four consecutive bytes supplied as
normal transmit data by the host processor. The sequence of bytes placed in the data stream to
implement this are:
Byte1
This must be equal to 80 hex to start a command sequence.
Byte 2
This byte indicates the required state of the ‘C’ lead to be synchronized with the
transmit data.
00 = set the ‘C’ lead to OFF
01 = set the ‘C’ lead to ON
02–FF = reserved, do not use
Byte 3
This is the required data character for transmission. It is sent as an 8-bit character
without parity (any required parity should be included in the character by the host).
Byte 4
This is the count of the number of times the character should be sent. If set to ‘0’, the
character is sent continuously until more data is provided to the transmitter (but
always a minimum of three times).
COR2 – Async-HDLC / PPP Mode
Register Name: COR2
Register Description: Channel Option Register 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
IXM
TxIBE
0
0
Bit 3
RLM
Intel Hex Address: x’14
Motorola Hex Address: x’17
Bit 2
RtsAO
Bit 1
CtsAE
Bit 0
DsrAE
120
Datasheet