CD2481 Datasheet, PDF (43/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
5.2.4.2
5.2.4.3
5.2.4.4
5.2.4.5
the PILR registers contain the same value and multiple IREQn* lines are asserted, the CD2481
imposes the following automatic priority scheme to determine which interrupt request will be
acknowledged:
Highest priority: Receive Interrupt register
Transmit Interrupt register
Lowest priority: Modem Interrupt register
Systems with Interrupt Controllers
Some systems use an interrupt controller that supplies its own vector during the interrupt
acknowledge cycle. The CD2481 needs an IACK cycle in response to its interrupt request to
function properly. These systems can decode three distinct locations for the CD2481 to produce an
IACKIN* instead of CS*. The PILR registers should be programmed with the least significant
seven bits of the addresses of these three locations.
Alternatively, a single location can be decoded and the three PILRs given identical values as
described above. In either case, the host should read one of these locations before the first access to
the device in an interrupt service routine. The CD2481 enters its interrupt context for the proper
type and channel, and the data returned is the device interrupt vector from the LIVR.
Multi-CD2481 Systems
Multiple CD2481s can be chained together for systems requiring more than four channels. Each
group of interrupt request lines — IREQn* — can be connected in a parallel, wired-OR fashion.
The system Interrupt Acknowledge signal is connected to the IACKIN* (Interrupt Acknowledge
In) pin of the first device, and its IACKOUT* (Interrupt Acknowledge Out) is then connected to
the IACKIN* of the next device, and so on, forming a chain of CD2481s.
Keep and Pass Logic
The acceptance of an interrupt acknowledge cycle by the CD2481 depends on whether the part is
requesting service and whether the least-significant seven address bits match the contents of the
appropriate PILR register. The following rules apply to the keep and pass logic:
1. If the CD2481 does not have an interrupt asserted, the interrupt acknowledge is passed out on
IACKOUT*.
2. If the CD2481 is asserting one or more of its interrupts, but the interrupt priority level driven
on the address bus by the host does not match the contents of the appropriate PILR register, the
interrupt acknowledge is also passed out on IACKOUT*.
3. If the CD2481 is asserting an interrupt, and the interrupt priority level on the address bus
matches the PILR register for that interrupt type, the interrupt acknowledge is accepted by the
CD2481, and the vector from the LIVR is driven onto the data bus.
Fair Share Scheme
When multiple CD2481s are chained, the Fair Share logic in these devices guarantees that the
interrupts from all CD2481s in the system are presented to the host with equal urgency. There is no
positional hierarchy in the interrupt scheme, that is, the CD2481 that is farthest from the host has
Datasheet
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