CD2481 Datasheet, PDF (105/222 Pages) Intel Corporation – Programmable Four-Channel Communications Controller

Programmable Four-Channel Communications Controller — CD2481
8.1
Global Initialization
The following is an example of global initialization. The host waits for a hardware reset,
determined by a non-zero value in the GFRCR (Global Firmware Revision Code register). After
the GFRCR becomes non-zero, the host must download the microcode image into the internal
SRAM (see chapter 5 for details of the download operation. After the download, a ‘Reset All’
command can be sent to the CD2481 by the CCR (Channel Command register). The internal CPU
puts a non-zero value into GFRCR when initialization is complete.
The PILRs (Priority Interrupt Level registers) should be loaded with the value of the seven address
lines A[6:0] during interrupt acknowledge cycles. The TPR (Timer Prescale register) loads the
dividing counter that inputs each of the other timers in the CD2481. The DMA Mode and Bus Error
Count registers are used in DMA modes only. After the Global portion is done, the Per-Channel
registers need to be initialized. Transfers and interrupts should be enabled after all other
initialization is complete.
// Global Initialization
while( !inportb( GFRCR ) )// wait for hardware reset
; // wait
outportb( CCR, RESET_ALL ) ;// Reset command
while( !inportb( GFRCR ) ) // wait for reset command
; // wait
outportb( PILR1, 0x02 );// Priority Interrupt
outportb( PILR2, 0x04 );// Level registers
outportb( PILR3, 0x06 );
outportb( TPR, 0x40 );// Set timer prescale
outportb( BERCNT, 0 );// Bus error count
outportb( DMR, 0 );// DMA mode — 16-bit
// per-channel initialization
for( i=0; i<4; i++ ) {
outportb( CAR, i );// set channel number
init_chan( cor, bpr );// initialize channel
outportb( CCR, INIT_CH | EN_RX | EN_TX );
Datasheet
105